Annotation
In this paper, the algorithm of error correction coding/decoding near the Shannon limit was implemented in FPGA (Fieldprogrammable gate array) for data rates up to 1 Gbit/s.
© 2016 Publisher M.V.Lomonosov Moscow State University
Authors
A.A. Seryakov, P.N. Zaharov, A.F. Korolev
Department of Photonics and Microwave Physics, Faculty of Physics, Lomonosov Moscow State University Moscow, 119991, Russia.
Department of Photonics and Microwave Physics, Faculty of Physics, Lomonosov Moscow State University Moscow, 119991, Russia.
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